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| (R) January 1998 N OT O REC O ED F END MM RN E N ESIG WD S HI-7152 10-Bit High Speed A/D Converter with Track and Hold Description The Intersil HI-7152 is a high speed 10-bit A/D converter which uses a Two-Step, Flash algorithm to achieve throughput rates of 200kHz. A unique switched capacitor technique allows a new input voltage to be sampled while a conversion is taking place. Internal high speed CMOS buffers at both the analog and reference inputs simplify external drive requirements. A Track and Hold amplifier is included on the chip, consisting of two high speed amplifiers and an internal hold capacitor. Microprocessor bus interfacing is simplified by the use of standard Chip Select, Read, and Write control signals. The digital three-state outputs are byte organized for interfacing the either 8-bit or 16-bit systems. An out-of-range pin, together with the MSB, can be used to indicate an underrange or over-range condition. The HI-7152 operates with 5V supplies. A single +2.5V reference is required to provide a bipolar input range from -2.5V to +2.5V. Features * Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5s * Continuous Throughput Rate . . . . . . . . . . . . . . . 200kHz * No Offset or Gain Adjustments Necessary * Internal Track and Hold Amplifier * Analog and Reference Inputs Fully Buffered * P Compatible Byte Organized Outputs * Low Power Consumption . . . . . . . . . . . . . . . . . . 150mW * Uses a Single 2.5V Reference for 2.5 V Input Range Applications * P Controlled Data Acquisition Systems * DSP - Avionics - Sonar * Process Control - Automotive Transducer Sensing - Industrial * Robotics * Digital Communications * Image Processing Ordering Information PART NUMBER HI3-7152J-5 HI3-7152K-5 HI3-7152A-9 HI3-7152B-9 HI1-7152S-2 LINEARITY (MAX. DLE) 1 LSB 1/2 LSB 1 LSB 1/2 LSB 1 LSB TEMP. RANGE (oC) 0 to 75 0 to 75 0 to 85 0 to 85 -55 to 125 PACKAGE 28 Ld PDIP 28 Ld PDIP 28 Ld PDIP 28 Ld PDIP 28 Ld CERDIP Pinout GND 1 V- 2 VREF 3 AG 4 VIN 5 SET 6 BUSY 7 CLK 8 HOLD 9 WR 10 CS 11 RD 12 SMODE 13 DG 14 HI-7152 (PDIP, CERDIP) TOP VIEW 28 V+ 27 OVR 26 D9 25 D8 24 D7 23 D6 22 D5 21 D4 20 D3 19 D2 18 D1 17 D0 16 HBE 15 BUS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 6-1 File Number 3100.1 HI-7152 Functional Diagram VREF REF AMP REF INVERT (+) (-) TWO STEP FLASH LATCHES AND OUTPUT BUFFERS DATA OUTPUTS 26 27 7 (1) BUS CTRL 15 16 D9 OVR BUSY BUS HBE (33) 17 D0 3 AG (ANALOG GROUND) 4 VIN (ANALOG INPUT) INPUT BUFFER AMP RESISTOR LADDER 5 TRACK HOLD AMP 9 V+ VGND HOLD 12 28 2 1 POWER SUPPLY DISTRIBUTION RD WR CS SMODE CLK SET 10 CONTROL LOGIC 11 13 8 6 DG 14 (DIGITAL GROUND) 6-2 HI-7152 Pin Descriptions PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SYMBOL GND VV REF AG V IN SET BUSY CLK HOLD WR CS RD SMODE DG BUS HBE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OVR V+ Ground return for comparators (0V). Negative supply voltage input (-5V). Reference voltage input (+2.50V). Analog ground reference (0V). Analog Input Voltage. Connect to V+ for proper operation. Output High-Conversion complete. Output Low - Conversion in progress. Output floats when chip is not selected (RD and CS both high). Clock input. Indicates start of conversion. Active low. Write input. With CS low, starts conversion when pulsed low; continuous conversions when kept low. Chip select input. Active low. Read input. With CS low, enables output buffers when pulsed low; outputs updated at end of conversion when kept low. Slow memory mode input. Active high. Digital ground (0V). Bus select input. High = all outputs enabled together D0 - D9, OVR. Low = outputs enabled by HBE. Byte select (HBE/LBE) input for 8-bit bus. Input high-High byte select, D8-D9, OVR Input low-low byte select, D0-D7. Bit 0 (Least significant, LSB). Bit 1. Bit 2. Bit 3. Bit 4. Bit 5. Bit 6. Bit 7. Bit 8. Bit 9 (Most Significant, MSB). Out of Range flag. Valid at end of conversion when output exceeds full scale. Positive supply voltage input (+5V). High Byte Output Data Bits (High = True) Low Byte DESCRIPTION 6-3 HI-7152 Absolute Maximum Ratings (Note 1) Supply Voltage V+ to Gnd (DG/AG/GND) . . . . . . . . . . . . . . . . -0.3V < V+ < +5.7V V- to Gnd (DG/AG/GND). . . . . . . . . . . . . . . . . .-5.7V < V- < +0.3V Analog Input Pins . . . . . . . . . . . . . . . . . V- -0.3V < VINA < V+ +0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . .DG - 0.3V < VI/O < V+ +0.3V Power Dissipation (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . <500mW Derate above 75oC at -10mW/C Thermal Information Thermal Resistance (Typical) JA ( oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . TBD N/A CERDIP Package . . . . . . . . . . . . . . . . TBD TBD Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range HI3-7152X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC HI3-7152X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltage provided the inputs current is limited to 1mA. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. Accuracy Electrical Specifications V+ = +5V, V- = -5V, VREF = 2.50V, fCLK = 600kHz, 50% Duty Cycle, Unless Otherwise Specified (Note 4) (NOTE 3) TEMP. (oC) TA = 25oC TMIN to TMAX ILE TA = 25oC TMIN to TMAX Differential Linearity Error DLE TA = 25oC TMIN to TMAX Bipolar Offset Error VOS TA = 25oC TMIN to TMAX Unadjusted Gain Error eG+ and eGTA = 25oC TMIN to TMAX J, A GRADE MIN 10 10 TYP 0.5 0.75 1.0 1.5 1.0 1.5 MAX 1.0 1.0 1.0 1.0 2.5 3.0 2.5 3.0 MIN 10 10 K, B GRADE TYP 0.3 0.5 0.6 1.0 0.6 1.0 MAX 0.5 0.75 0.5 0.75 1.5 2.0 1.5 2.0 UNITS Bits Bits LSB LSB LSB LSB LSB LSB LSB LSB PARAMETER Resolution (Note 5) (With no missing codes) Integral Linearity Error SYMBOL RES NOTES: 3. See Ordering Information Table. 4. FSR (Full Scale Range) = 2 X V REF (5V at VREF = 2.5V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.5V). DC Electrical Specifications V+ = 5V, V- = -5V, VREF = 2.50V, TA = 25oC, fCLK = 600kHz, 50% Duty Cycle, Unless Otherwise Specified (NOTE 5) TEST CONDITION VIN = 0V 25oC MIN -VREF TYP 0.01 8 MAX VREF 100 20 0oC to 75oC MIN -VREF MAX VREF 100 -40oC to 85oC MIN -VREF MAX VREF 100 UNITS V nA pF PARAMETER ANALOG INPUT Analog Input Range Analog INput Bias Current Analog Input Capacitance (Note 6) REFERENCE INPUT Reference Input Range (Note 7) Reference Input Bias Current Reference Input Capacitance (Note 6) SYMBOL VIR IBI CVIN VRR IBR CVR VREF = 2.50V 2.2 - 2.5 0.01 7 2.6 100 20 2.2 - 2.6 100 - 2.2 - 2.6 100 - V nA pF 6-4 HI-7152 DC Electrical Specifications V+ = 5V, V- = -5V, VREF = 2.50V, TA = 25oC, fCLK = 600kHz, 50% Duty Cycle, Unless Otherwise Specified (Continued) (NOTE 5) TEST CONDITION FIN = 100kHz 25oC MIN VIH VIL IIL CIN VOH VOL IOL COUT V+ VeGVS IOH = -200A IOL = 1.6mA RD = V+, VOUT = V+ RD = V+, VOUT = 0V Output Capacitance (Note 6) (Note 8) (Note 8) POWER SUPPLY REJECTION V+, V- Gain Coefficient V+ = 5V, V- = -4.75V, -5.25V V- = -5V, V+ = 4.75V, 5.25V V+, V- Offset Coefficient VOSVS V+ = 5V, V- = -4.75V, -5.25V V- = -5V, V+ = 4.75V, 5.25V SUPPLY CURRENTS V+ Supply Current V- Supply Current GND Current DG Current AG Current I+ IIGND IDG IAG V+ = 5V 10% V- = -5V 10% VIN = 0V, Digital Outputs are Unloaded 20 -10 -8 -2 0.02 30 -15 30 -15 30 -15 mA mA mA mA A 0.1 0.1 0.1 0.1 0.05 0.5 0.5 0.5 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 LSB LSB LSB LSB High-Z State Function Operation Only POWER SUPPLY VOLTAGE RANGE 4.5 -4.5 5.0 -5.0 5.5 -5.5 4.5 -4.5 5.5 -5.5 4.5 -4.5 5.5 -5.5 V V VIN = 0V, V+ 2.0 2.4 -1 TYP 9 1.5 30 2 -80 1.5 0.05 5 0.04 -0.01 7 MAX 0.8 1 17 0.4 1 15 0oC to 75oC MIN 2.0 2.4 -10 MAX 0.8 1 0.4 10 -40oC to 85oC MIN 2.0 2.4 -10 MAX 0.8 1 0.4 10 UNITS V/s MHz ns ns dB s V V A pF V V A A pF PARAMETER TRACK AND HOLD (See Text) Slew Rate Bandwidth Aperture Time Aperture Uncertainty Feedthrough in HOLD Acquisition Time LOGIC INPUTS Input High Voltage Input Low Voltage Logic Input Current Input Capacitance (Note 6) LOGIC OUTPUTS Output High Voltage Output Low Voltage Output Leakage Current SYMBOL SR BW NOTES: 5. FSR (Full Scale Range) = 2 X V REF (5V at VREF = 2.5V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.5V). 6. Parameter not tested. Parameter guaranteed by design, simulation, or characterization. 7. Only VOS and GAIN ERROR functionality tested at 2.2V and 2.6V. 8. Guaranteed by functionality test. 6-5 HI-7152 AC Electrical Specifications V+ = 5V 10%, V- = -5V 10%, VREF = 2.5V, TA = 25oC, fCLK = 600kHz, 50% Duty Cycle, C L = 100pF (including stray for D0 - D9, OVR, HOLD, BUSY), Unless Otherwise Specified (Note 12) 25oC PARAMETER Continuous Conversion Time SYMBOL tSPS NOTES 10 10 Slow Memory Mode Conversion Time Continuous Throughput CLOCK Period Clock Input Duty Cycle CLOCK to HOLD Rise Delay WR Pulse Width WR to HOLD Delay Busy to Data WR to RD Active CLOCK to HOLD Fall Delay HOLD to DATA Change RD LO to Active RD HI to Inactive HBE to DATA CS to DATA RD to BUSY Rise Time Fall Time NOTES: 9. Slow memory mode timing. 10. Fast memory or DMA mode of operation, except the first conversion which is equal to tCONV . 11. Maximum specification to prevent multiple triggering with WR. 12. All input drive signals are specified with tr = tf 20ns and shall swing from VIL -0.4V to V IH +0.4V for all timing specifications. A signal is considered to change state as it crosses a 1.4V threshold (except tRD and tRX). 13. tr and tf load is CL = 100pF (including stray capacitance) to DG and is measured from the 10 - 90% point. 14. tRD is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. High-Z to VOH is measured with RL = 2.5k and C L = 100pF (including stray) to DG. High-Z to VOL is measured with RL = 2.5k to V+ and CL = 100pF (including stray) to DG. 15. tRX is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. VOH to High-Z is measured with RL = 2.5k and CL = 10pF (including stray) to DG. VOL to High-Z is measured with RL = 2.5k to V+ and CL = 10pF (including stray) to DG. tCONV tCYC tCK D tCKHR tWRL tHOLD tBD tWRD tCKHF tDATA tRD tRX tAD tCD tBUSY tr tf 6, 9 MIN 60 TYP MAX 3tck 5 4tck +0.9 fCLK /3 55 500 tck/2 170 200 250 400 150 60 150 180 200 100 100 0oC to 75oC MIN 60 MAX 3tck 5 4tck +0.9 fCLK /3 55 525 tck/2 200 230 275 550 190 80 165 210 200 125 120 -40oC to 85oC MIN 60 MAX 3tck 10 4tck +0.9 fCLK /3 55 525 tck/2 200 230 275 550 190 80 165 210 200 125 120 % ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNITS s s s 10 6 6 6, 9, 11 6, 9 6, 9 6, 9 6, 10 6, 10 6, 14 6, 15 6 6 6 6, 13 6, 13 45 150 200 100 50 100 - 1/fCLK 50 290 113 80 40 125 200 75 25 70 95 35 50 45 45 140 225 100 40 90 - 45 120 225 100 25 70 - sps 6-6 HI-7152 Timing Diagrams SMODE = +V, BUS = V+, HBE = V+ OR DG 0 CLOCK 1 tCK 2 3 4 5 6 7 CS WR tWRL HOLD TRACK N INTERNAL DATA RD HOLD N tHOLD N DATA tCKHR TRACK N+1 tWRD tBUSY tBD BUSY D0-D9, OVR DATA N DATA tCONV FIGURE 1A. SLOW MEMORY MODE (16-BIT DATA BUS) 6-7 HI-7152 Timing Diagrams (Continued) SMODE = DG, BUS = DG 0 CLOCK tCD CS tSPS tCKHF TRACK N+1 HOLD N+1 tDATA INTERNAL DATA RD HBE (HBE/LBE) N DATA N+1 DATA tCKHR TRACK N+2 HOLD N+2 TRACK N+3 1 2 3 4 5 6 7 WR (WR MAY BE WIRED LOW) tHOLD HOLD N HOLD TRACK N tRD tAD D0-D9, OVR DATA BUSY tRX LOW BYTE HIGH BYTE N+1 DATA LOW BYTE HIGH BYTE N DATA FIGURE 1B. FAST MEMORY MODE (8-BIT DATA BUS) SMODE = +V: RD, WR, AND CS = DG, BUS = V+, HBE = V+ OR DG 0 CLOCK 1 2 3 4 5 6 7 HOLD TRACK N HOLD N TRACK N+1 HOLD N+1 TRACK N+2 HOLD N+2 INTERNAL DATA N-1 DATA N DATA N+1 DATA BUSY D0-D9, OVR DATA N-1 DATA N DATA N+1 DATA FIGURE 1C. DMA MODE (16-BIT DATA BUS) Detailed Block Diagram (+VREF) 5 TO 32 DECODER VREF 3 + () AZ AZ AZ AZ 33 AZ 6-8 LATCH 17 DO HI-7152 Detailed Description The HI-7152 is a high speed 10-bit A/D converter which achieves throughput rates of 200kHz by use of a Two Step Flash algorithm. A pipelined operation has been achieved through the use of switched capacitor techniques which allow the device to sample a new input voltage while a conversion is taking place. The HI-7152 requires a single reference input of +2.5V, which is internally inverted to 2.5V, thereby allowing an input range of -2.5V to +2.5V. 10 bits including sign are two's complement coded. The analog and reference inputs are internally buffered by high speed CMOS buffers, which greatly simplifies the external analog drive requirements for the device. The 5-bit result of the first flash conversion is latched into the upper five bits of double buffered latches. It is also converted back into an analog signal by choosing the ladder voltage which is closest to but less than the input voltage. The selected voltage (VTAP) is then subtracted from the input voltage. This residue is amplified by a factor of 32 and referenced to the negative reference voltage (VSCA = (VIN - VTAP) X 32 + VREF -). This subtraction and amplification operation is performed by a Switched Capacitor Amplifier (SCA). The output of the SCA falls between the positive and negative reference voltages and can therefore be digitized by the original 5-bit flash converter (second flash conversion). The 5-bit result of the second flash conversion is latched into the lower five bits of double buffered latches. At the end of a conversion, 10 bits of data plus an Out of Range bit are latched into the second level of latches and can then be put on the digital output pins. The conversion takes place in three clock cycles and is illustrated in Figure 3. When the conversion begins, the track and hold goes into its hold mode for 1 clock cycle. During the first half clock cycle the comparator array is in its auto-zero mode and it samples the input voltage. During the second half clock cycle, the comparators make a comparison between the input voltage and the ladder voltages. At the beginning of the third half clock cycle, the first most significant 5-bit result becomes available. During the first clock cycle, the SCA was sampling the input voltage. After the first flash result becomes available and a ladder tap voltage has been selected the SCA amplifies the residue between the input and ladder tap voltages. During the next three half clock cycles, while the SCA output is settling to its required accuracy, the comparators go into their auto-zero mode and sample this voltage. During the sixth half clock cycle, the comparators perform another comparison whose 5-bit result becomes available on the next clock edge. A/D Section The HI-7152 uses a conversion algorithm which is generally called a "Two Step Flash" algorithm. This algorithm enables very fast conversion rates without the penalty of high power dissipation or high cost. A detailed functional diagram is presented in Figure 2. The input voltage is first converted into a 5-bit result (plus Out of Range information) by the flash converter. This flash converter consists of an array of 33 auto-zeroed comparators which perform a comparison between the input voltage and subdivisions of the reference voltage. These subdivisions of the reference voltage are formed by forcing the reference voltage and its negative on the two ends of a string of 32 resistors. The reference input to the HI-7152 is buffered by a high speed CMOS amplifier which is used to drive one end of the resistor string. Another high speed amplifier configured in the inverting unity gain mode inverts the reference voltage with respect to analog ground and forces in onto the other end of the resistor string. Both reference amplifiers are offset trimmed at the factory in order to increase the accuracy of the HI-7152 and to simplify its usage. N CONVERSION CLOCK 1 2 3 4 5 6 N + 1 CONVERSION TRACK AND HOLD HOLD VIN(N) CONVERT UPPER 5 BITS TRACK VIN(N + 1) CONVERT LOWER 5 BITS HOLD VIN (N + 1) COMPARATOR AUTO-ZERO (AZ) SCA AUTO-ZERO (SCAZ) SAMPLE VIN(N) SAMPLE RESIDUAL SAMPLE VIN(N + 1) SAMPLE VIN(N) AMPLIFY RESIDUAL SAMPLE VIN(N + 1) INTERNAL DATA 10-BITS + OVR VIN (N) DATA FIGURE 3. INTERNAL ADC TIMING DIAGRAM 6-9 HI-7152 TABLE 1. A/D OUTPUT CODE TABLE ANALOG INPUT (NOTE) LSB = 2 (VREF) / 1024 +VREF +VREF - 1 LSB +1 LSB 0 -1 LSB -VREF -VREF - 1 LSB VREF = 2.500V 2.500V to V+ (+OVR) 2.49512V (+Full Scale) 0.00488V 0.000V -0.00488V -2.500V (-Full Scale) -2.50488V to V- (-OVR) OVR 1 0 0 0 0 0 1 MSB 9 0 0 0 0 1 1 1 8 0 1 0 0 1 0 0 7 0 1 0 0 1 0 0 OUTPUT DATA 6 0 1 0 0 1 0 0 5 0 1 0 0 1 0 0 4 0 1 0 0 1 0 0 3 0 1 0 0 1 0 0 2 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 LSB 0 0 1 1 0 1 0 0 NOTE: The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. Track and Hold Analog Input A Track and Hold amplifier has been fully integrated on the front end of the A/D converter. Because of the sampling nature of this A/D converter, the input is required to stay constant only during the first clock cycle. Therefore, the Track and Hold (T/H) amplifier "holds" the input voltage only during the first clock cycle and it acquires the input voltage for the next conversion during the remaining two clock cycles. The high input impedance of the T/H input amplifier simplifies analog interfacing. Input signals up to VREF can be directly connected to the A/D without buffering. The A/D output code table is shown in Table 1. The timing signals for the Track and Hold amplifier are generated internally, and are also provided externally (HOLD) for synchronization purposes. The T/H amplifier consists of two high speed CMOS amplifiers and an internal hold capacitor. Its typical slew rate and bandwidth are 9V/s and 1.5MHz respectively. It is configured to give a very small hold pedestal without the use of an external hold capacitor. The hold pedestal is typically less than 100V. Acquisition of the analog input signal is the time required by the T/H for its output to reach its final value within a specified error band. This time is a function of the logic delay time, op amp slewing time, and settling time. The T/H is in the track mode for 2 clock cycles (3.3s at CLK = 600kHz) but the output typically settles to within 1/4 LSB in 1.5s. Aperture delay time is the time required for the T/H switch to open following the internal hold command. This is the delay with respect to falling edge of WR and the internal hold command. It is equal to THOLD (type) - 50ns (Typ) which is typically 30ns. Aperture uncertainty (jitter) is a range of variation in the aperture time. The greater the aperture time the larger the uncertainty in the analog voltage being converted. If the aperture time is nulled out by advancing the hold command (WR) or the signal is repetitively sampled, aperture uncertainty becomes the major source of time error. The aperture uncertainty for the T/H is typically 2ns which sets the maximum input bandwidth to 77.7kHz for 1 LSB resolution. fMAX = 1/(2 x 2n x ta) where n = resolution in bits ta = aperture uncertainty All of the internal amplifiers are offset trimmed during manufacturing to give improved accuracy and to minimize the number of external components. If necessary, offset error can be adjusted either at an external interface buffer or by using digital post correction. Reference Input The reference input to the HI-7152 is buffered by a high speed CMOS amplifier. The reference input range is 2.2V to 2.6V. Power Requirements Power to the chip should be applied in the following order: V-, V+, and VREF . In applications where V+ is supplied prior to V-, the positive supply current will be approximately 2 times its nominal value until V- is applied (this is not a latchup condition). Initialization In fast memory and DMA modes (after proper power, VREF , and clock) up to 6 clock cycles are required for circuit initialization. After circuit initialization, valid data will be available in 3 clock cycles. Microprocessor Interface The HI-7152 can be interfaced to microprocessors through the use of standard Write, Read, Chip Select, and HBE control pins. The digital outputs are two's complement coded, three-state gated, and byte organized for bus interface with 8-bit and 16-bit systems. The digital outputs (D0 D9, OVR, and BUSY) may be accessed under control of BUS, byte enable input HBE, chip select, and read inputs for a simple parallel bus interface. The microprocessor can read the current data in the output latches in typically 75ns/byte (trd). An over range pin (OVR) together with the MSB (D9) pin set to either a logic 0 or 1 will indicate a positive or negative over-range condition respectively. All digital output buffers are capable of driving one TTL load. The HI-7152 can be interfaced to a microprocessor using one of three modes: slow memory, fast memory, and DMA mode. 6-10 HI-7152 Slow Memory Mode In slow memory mode, the conversion will be initiated by the microprocessor by selecting the chip (CS) and pulsing WR low. This mode is selected by hardwiring the SMODE pin to V+. This mode is intended for use with microprocessors (such as the 8086) which can be forced into a WAIT state. For example, in configuration where the BUSY output is tied to the 8086 READY input, an attempt to read the data before the conversion is complete will force the processor into a WAIT state until BUSY goes high, at which time the data at the output is valid. This resembles a 5s access time RAM. It allows the processor to initiate a conversion, WAIT, and READ data with a single READ instruction. When the 8-bit bus operation is selected, high and low byte data may be accessed in either order. An I/O truth table is presented in Table 2 for the slow memory mode of operation. TABLE 2. SLOW MEMORY MODE I/O TRUTH TABLE (SMODE = V+) CS 0 1 0 0 0 X WR 0 X X X X X RD X X 0 0 0 1 BUS HBE X X 1 0 0 X X X X 0 1 X FUNCTION Initiates a Conversion. Disables All Chip Commands. D0 - D9 and OVR Enabled. Low Byte Enabled: D0 - D7. High Byte Enabled: D8 - D9, OVR. Disables all Outputs (High Impedance). TABLE 3. FAST MEMORY MODE I/O TRUTH TABLE (SMODE = DG) CS X 1 0 0 0 X WR 0 X X X X X RD X X 0 0 0 1 BUS HBE X X 1 0 0 X X X X 1 0 X FUNCTION Continuous Conversion, WR may be Tied to DG. Disables Only the RD Command. D0 - D9 and OVR Enabled. High Byte Enabled: D8 - D9, OVR (Enable 1st). Low Byte Enabled: D0 - D7 (Must Enable 2nd). Disables All Outputs (High Impedance). NOTE: X = Don't Care DMA Mode This mode is a complete hardware mode where the HI-7152 continuously converts. The user implements hardware to store the results in memory, bypassing the microprocessor. This mode is recognized by the chip when SMODE is hardwired to V+ and CS, RD, WR are hardwired to DG. When 8-bit bus operation is selected, high and low byte data may be accessed in either order. BUSY is continuously low when accessed with a read command in this mode. An I/O truth table is presented in Table 4 for the DMA mode of operation. TABLE 4. DMA MODE I/O TRUTH TABLE (SMODE = V+, CS = WR, RD = DG) BUS 1 0 0 HBE X 0 1 FUNCTION D0 - D9 and OVR Enabled. Low Byte Enabled: D0 - D7. High Byte Enabled: D8 - D9, OVR. NOTE: X = Don't Care Fast Memory Mode The fast memory mode of operation is selected by tying the SMODE and WR pins to DG. In this mode, the chip performs continuous conversions and only CS and RD are required to read the data. Whenever the SMODE pin is low, WR is independent of CS in starting a conversion cycle. During the first conversion cycle, HOLD follows WR going low. Data can be read a byte at a time or all 11 bits at once. The internal logic disables the output latches from being updated during a read after the high byte data is accessed. It will continue to be disabled until after the low byte data is accessed. THEREFORE, WHEN 8-BIT BUS OPERATION IS SELECTED, THE DATA MUST BE ACCESSED HIGH BYTE FIRST, LOW BYTE NEXT. If the low byte is accessed first followed by high byte, the results from the next conversion cycle will be lost because the updating of the output latch is disabled. BUSY is continuously low when accessed with a read command in this mode. An I/O truth table is presented in Table 3 for the fast memory mode of operation. The data can be defined in time by monitoring the HOLD pin. The conversion data can be read after HOLD has gone low. NOTE: X = Don't Care Optimizing System Performance The HI-7152 has three ground pins (AG, DG, GND) for improved system accuracy. Proper grounding and bypassing is illustrated in Figure 4. The AG pin is a ground pin that does not carry any current and is used internally as a reference ground. The reference input and analog input should be referenced to the analog ground (AG) pin. The digital inputs and outputs should be referenced to the digital ground (DG) pin. The GND pin is a return point for the supply current of the comparator array. The comparator array is designed such that this current is approximately constant at all times and does not vary with input voltage. By virtue of the switched capacitor nature of the comparators, it is necessary to hold GND firmly at zero volts at all times. Therefore, the system ground star connection should be located as close to this pin as possible. 6-11 HI-7152 As in any analog system, good supply bypassing is necessary in order to achieve optimum system performance (minimize conversion errors). The power supplies should be bypassed with at least a 20F tantalum and 0.1F ceramic capacitors to GND. The reference input should be bypassed with a 0.1F ceramic capacitor to AG. The capacitor leads should be as short as possible. The pins on the HI-7152 are arranged such that the analog pins are well isolated from the digital pins. In spite of this arrangement, there is always pin to pin coupling. Therefore the analog inputs to the device should not be driven from very high output impedance sources. PC board layout should screen the analog and reference inputs with AG. Using a soldier mask is good practice and helps reduce leakage due to moisture contamination on the PC board. Figure 8 illustrates an application where the HI-7152 is used with an analog multiplexer to form a multi-channel data acquisition system. Either slow memory or fast memory modes of operation can be selected. Fast memory mode should be selected for maximum throughput. Multiplexer channel acquisition should occur approximately 500ns after HOLD goes high. This allows 2 clocks minus 0.5s for the input to settle. With a 600kHz clock the input has up to 2.8s to settle. An intelligent system which performs a scale factor adjustment under software control with the addition of a programmable gain block between the multiplexer and HI-7151 is illustrated in Figure 9. The microprocessor first performs a conversion and then checks the over-range status (OVR) bit. If the OVR bit is high, the microprocessor addresses a precision gain circuit for scale factor adjustment and initiates another conversion. The microprocessor must keep track of the selected scale factor. The accuracy of the programmable gain amplifier should be better than 0.05%. For optimum system performance, op amp frequency response, settling time, and charge injection of the analog switch must be considered. Figure 10 illustrates the HI-7152 interfaced to FIFO memories for use in DMA applications. Applications Typical applications are illustrated in Figure 5 through 7 for the slow memory, fast memory, and DMA modes of operation. The output data is configured for 16-bit bus operation of these three applications. By tying BUS and DG and connecting the HBE input to the system address decoder, the output data can be configured for 8-bit bus systems. 20F 0.1F + 2.5V P.S. + -5V P.S. HI-7152 0.1F 20F 1 GND 2 V3 VREF 4 AG 5 VIN 6 SET 7 BUSY 8 CLK 9 HOLD 10 WR 11 CS 12 RD 13 SMODE 14 DG V+ 28 OVR 27 D9 26 D8 25 D7 24 D6 23 D5 22 D4 21 D3 20 D2 19 D1 18 D0 17 HBE 16 BUS 15 5V P.S. + - - 0.1F ANALOG INPUT V+ FIGURE 4. GROUND AND POWER SUPPLY DECOUPLING 6-12 HI-7152 HI-7152 1 GND ADDRESS BUS -5V +2.56V 0V ANALOG INPUT V+ 2 V3 VREF 4 AG 5 VIN 6 SET 7 BUSY 600kHz CLOCK 8 CLK 9 HOLD 10 WR 11 CS 12 RD 13 SMODE 14 DG V+ 28 OVR 27 D9 26 D8 25 16-BIT DATA BUS D7 24 D6 23 D5 22 D4 21 D3 20 D2 19 D1 18 D0 17 HBE 16 BUS 15 +5V CS WR HOLD TRACK N INTERNAL DATA RD WR LINE RD LINE READY HOLD N TRACK N+1 N DATA BUSY D0-D9, OVR DATA N DATA FIGURE 5. SLOW MEMORY MODE APPLICATION 6-13 HI-7152 HI-7152 1 GND ADDRESS BUS -5V +2.56V 0V ANALOG INPUT V+ 2 V3 VREF 4 AG 5 VIN 6 SET 7 BUSY 600kHz CLOCK 8 CLK 9 HOLD 10 WR 11 CS 12 RD 13 SMODE 14 DG V+ 28 OVR 27 D9 26 D8 25 16-BIT DATA BUS HOLD N+2 D7 24 D6 23 D5 22 D4 21 D3 20 D2 19 D1 18 D0 17 HBE 16 BUS 15 +5V RD LINE CS DATA WR (WR MAY BE WIRED LOW) HOLD INTERNAL DATA RD D0-D9, OVR DATA TRACK N HOLD N TRACK N+1 HOLD N+1 TRACK N+2 TRACK N+3 N DATA N+1 DATA N DATA BUSY N+1 DATA FIGURE 6. FAST MEMORY MODE APPLICATION 6-14 HI-7152 HI-7152 1 GND -5V +2.56V 0V ANALOG INPUT V+ 2 V3 VREF 4 AG 5 VIN 6 SET 7 BUSY 600kHz CLOCK 8 CLK 9 HOLD 10 WR V+ 11 CS 12 RD 13 SMODE 14 DG V+ 28 OVR 27 D9 26 D8 25 16-BIT DATA BUS TRACK N+2 D7 24 D6 23 D5 22 D4 21 D3 20 D2 19 D1 18 D0 17 HBE 16 BUS 15 +5V HOLD INTERNAL DATA D0-D9, OVR TRACK N HOLD N TRACK N+1 HOLD N+1 HOLD N+2 N-1 DATA 5s N DATA N+1 DATA FIGURE 7. DMA MODE APPLICATION ADDRESS BUS ADDRESS DECODER ANALOG INPUTS S1 S2 S3 S4 S5 S6 S7 S8 WR V+ VDG RS SYSTEM RESET A0-A2, EN VIN +2.56V SIGNAL GROUND +5V -5V VREF AG V+ VDG GND D0-D7 HI-7152 ADC (SLOW MEMORY MODE) ADDRESS DECODER DG BUS HBE CS RD DG528 MUX WR SMOD HOLD BUSY CLK SET 600kHz CLOCK V+ V+ MICROPROCESSOR D8-D9, OVR 8-BIT DATA BUS FIGURE 8. MULTI-CHANNEL DATA ACQUISITION SYSTEM 6-15 HI-7152 ADDRESS BUS ADDRESS DECODER ANALOG INPUTS S1 S2 S3 S4 S5 S6 S7 S8 CS WR D V+ VDG PROGRAMMBLE GAIN AMP +2.56V SIGNAL GROUND +5V -5V VIN VREF AG V+ VDG GND D0-D7 HI-7152 ADC (SLOW MEMORY MODE) ADDRESS DECODER DG BUS HBE CS RD DG528 MUX WR SMOD HOLD BUSY CLK SET 600kHz CLOCK V+ V+ MICROPROCESSOR RS SYSTEM RESET D0-D2, EN D8-D9, OVR 8-BIT DATA BUS FIGURE 9. MULTI-CHANNEL DATA ACQUISITION SYSTEM WITH PROGRAMMABLE GAIN V+ VIN VREF AG +5V -5V V+ VDG GND HI-7152 ADC BUS HBE SMODE D8-D9, OVR SET CLK HOLD V+ 600kHz BUSY RD WR CS DG D0-D3 64 x 4-BIT FIFO TO PARALLEL DATA BUS ANALOG INPUT +2.56V SIGNAL GROUND D4-D7 64 x 4-BIT FIFO COMPOSITE OUTPUT READY D8-D9, OVR 64 x 4-BIT FIFO SHIFT OUT SHIFT IN FIGURE 10. DMA/FIFO DATA ACQUISITION SYSTEM 6-16 |
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